Semiconductor device having an insulated gate and a fabrication process thereof

ABSTRACT

A semiconductor device includes a T-shaped gate on a gate insulation film, wherein the T-shaped gate includes a lower polycrystal layer containing Si and Ge and an upper polycrystal layer of polysilicon.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application is based on Japanese priority applicationNo.2000-210793 filed on Jul. 12, 2001, the entire contents of which arehereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention generally relates to semiconductor devicesand more particularly to a semiconductor device having an insulated gateelectrode and a fabrication process thereof.

[0003] With the progress in the art of device miniaturization,semiconductor devices forming an advanced high-speed LSIs or advancedmemory LSIs are now having a gate length approaching the value of 0.1μm.

[0004] In such highly miniaturized, high-speed semiconductor devices,there emerges a problem of signal delay caused by a parasiticcapacitance that is formed at the part of the semiconductor device inwhich a diffusion region formed adjacent to a gate electrode invadesinto the region right underneath the gate electrode in the form ofextension of the diffusion region.

[0005] In order to minimize such an overlap of the extension region,there is proposed a MOSFET that uses a T-shaped gate electrode.

[0006]FIG. 1 shows the construction of a conventional MOSFET having sucha T-shaped gate.

[0007] Referring to FIG. 1, the MOSFET is constructed on a p-type Sisubstrate 41 and includes a T-shaped gate electrode 43 provided on theSi substrate 41 with a gate oxide film 42 interposed between the Sisubstrate 41 and the gate electrode 43.

[0008] At both lateral sides of the T-shaped gate electrode, there areformed n-type extension regions 44 formed by an ion implantation processof an impurity element such as As, wherein the ion implantation processfor forming the extension regions 44 is conducted while using the toppart of the T-shaped gate electrode 43 as a mask.

[0009] After formation of the n-type extension regions 44, sidewallinsulation films (not shown) are provided on both lateral sidewalls ofthe gate electrode 43, and n⁺-type diffusion regions 45 are formed inthe substrate 41 in the region outside the sidewall insulation films byan ion implantation process of an impurity element such as As whileusing the sidewall insulation films as a mask.

[0010] According to the foregoing process, the extension regions 44 areformed initially with an offset from the bottom lateral edge of the gateelectrode, due to the fact that the ion implantation for forming theextension regions 44 has been conducted while using the top part of theT-shaped gate electrode 43 as a mask. This offset, however, disappearsas the thermal annealing process for activating the introduced As ionsis conducted, and the extension part 44 has a tip end generallycoincident to the bottom lateral edge of the T-shaped gate electrode 43in the state of FIG. 1 in which the thermal annealing process has beenconducted.

[0011] On the other hand, the structure of FIG. 1 has a drawback, due tothe use of the T-shaped gate electrode, in that the control of theprocess is difficult. Particularly, it has been necessary to use acomplex process for forming the T-shaped gate electrode.

[0012] More specifically, it has been necessary to apply a lateraletching process to a gate electrode patterned according to an ordinaryprocess, with such a condition that the lateral etching process actspreferentially upon the bottom part of the gate electrode with respectto the gate insulation film. However, control of such a lateral etchingprocess is difficult.

[0013] Further, there arises a problem in the MOSFET of FIG. 1 in that Bintroduced into the gate electrode 43 may invade into the channel regionof the MOSFET across the gate insulation film 42 at the time of thermalannealing process for activating the impurity elements introduced by theion implantation process. When such invasion of B occurs in the channelregion, the threshold characteristic of the MOSFET is inevitablymodified.

[0014] One way to avoid this modification of the thresholdcharacteristic of MOSFET would be to reduce the temperature used for thethermal activation process of the impurity element. However, the use ofsuch a low thermal activation temperature results in insufficientactivation of the doped impurity elements, and there can occur theformation of depletion region in the gate region adjacent to the gateinsulation film as a result of the insufficient activation of theimpurity elements.

SUMMARY OF THE INVENTION

[0015] Accordingly, it is a general object of the present invention toprovide a novel and useful semiconductor device having an insulated gateand fabrication process thereof wherein the foregoing problems areeliminated.

[0016] Another and more specific object of the present invention is toprovide a semiconductor device having a T-shaped insulated gate whereinthe problem of penetration of B across a gate insulation film iseliminated.

[0017] Another object of the present invention is to provide a simpleand reliable process for fabricating a semiconductor device having aT-shaped insulated gate.

[0018] Another object of the present invention is to provide asemiconductor device, comprising:

[0019] a substrate including a semiconductor layer at least on a toppart thereof;

[0020] a gate insulation film provided on said semiconductor layer; and

[0021] a gate electrode provided on said gate insulation film,

[0022] said gate electrode comprising a first polycrystal layer incontact with said gate insulation film, said first polycrystal layercontaining at least Si and Ge, and a second polycrystal layer providedon said first polycrystal layer,

[0023] said first polycrystal layer having a reduced lateral size ascompared with said second polycrystal layer, said first and secondpolycrystal layers thereby forming a T-shaped gate electrode.

[0024] Another object of the present invention is to provide a method offabricating a semiconductor device, comprising the steps of:

[0025] forming a gate insulation film on a substrate, said substrateincluding a semiconductor layer at least on a top part thereof;

[0026] depositing a first polycrystal layer containing at least Si andGe on said semiconductor layer;

[0027] depositing a second polycrystal layer of Si on said firstpolycrystal layer;

[0028] patterning said first and second polycrystal layers to form agate electrode defined by a pair of sidewalls; and

[0029] applying an oxidation process to said first and secondpolycrystal layers such that said first and second polycrystal layersundergo oxidation at said both sidewalls.

[0030] According to the present invention, the penetration of B into thechannel region of the semiconductor device through the gate insulationfilm is effectively blocked by interposing the SiGe first polycrystallayer between the gate insulation film and the second polycrystal layer.As a result, the semiconductor device provides a stable thresholdcharacteristic. As a result of the use of the T-shaped gate electrode,the problem of penetration of the extension region of the diffusionregion into the channel region right underneath the gate electrode ispositively eliminated, and the semiconductor device of the presentinvention provides a high operational speed.

[0031] Further, the use of the SiGe first polycrystal layer facilitatesformation of the T-shaped electrode due to the accelerated oxidationrate as compared with an ordinary polysilicon layer. More specifically,the desired T-shaped gate electrode is formed easily in a singleoxidation step.

[0032] Other objects and further features of the present invention willbecome apparent from the following detailed description when read inconjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1 is a diagram showing the construction of a MOSFET accordingto a related art;

[0034]FIG. 2 is a diagram showing the construction of a MOSFET showingthe principle of the present invention;

[0035] FIGS. 3A-3F are diagrams showing the fabrication process of aMOSFET according to a first embodiment of the present invention;

[0036] FIGS. 4A-4C are diagrams showing the fabrication process of aMOSFET according to a second embodiment of the present invention;

[0037] FIGS. 5A-5C are diagrams showing the fabrication process of aMOSFET according to a third embodiment of the present invention; and

[0038]FIG. 6 is a diagram showing the construction of a MOSFET accordingto a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0039] [Principle]

[0040]FIG. 2 shows the principle of the present invention.

[0041] Referring to FIG. 2 showing a MOSFET of the present invention,the MOSFET is constructed on semiconductor substrate 1 formed therein apair of diffusion regions 8 having respective extension regions 7,wherein the extension regions 7 define therebetween a channel region.

[0042] On the substrate 1, there is provided a gate insulation film 2 incorrespondence to the channel region and a polycrystal layer 3 of SiGeis provided on the gate insulation film 2 in contact therewith. Further,a polysilicon layer 4 is provided on the polycrystal layer 3 with anincreased lateral width, wherein the polysilicon layer 4 form, togetherwith the polycrystal layer 3, a T-shaped gate electrode.

[0043] It should be noted that the T-shaped gate electrode is actuallyformed by a lateral oxidation process applied to the polycrystal layer 3and further to the polysilicon layer 4, wherein such an oxidationprocess proceeds with a greater rate in the polycrystal layer 3 thatcontains Ge in addition to Si as compared with the polysilicon layer 4.As a result, the T-shape gate electrode carries a lateral oxide film 5on both lateral sides thereof such that the lateral oxide film 5 has anincreased thickness in the part thereof covering the sidewall of thepolycrystal layer 3 as compared with the part covering the sidewall ofthe polysilicon layer 4.

[0044] In the structure of FIG. 2, the extension region 7 is formed byintroducing an impurity element by an ion implantation process whileusing the lateral oxide film 5 as a mask. Further, the diffusion regions8 are formed in the substrate 8 by an ion implantation process whileusing sidewall insulation films 6 provided on the lateral oxide film 5as a mask.

[0045] As a result of the use of the SiGe polycrystal layer 3 betweenthe polysilicon layer 4 and the gate insulation film 2, the problem ofpenetration of B contained in the polysilicon layer 4 into the channelregion across the gate insulation film 2 is effectively eliminated, andthe MOSFET of FIG. 2 shows a stabilized threshold characteristic.

[0046] Further, the MOSFET of FIG. 2 shows an advantageous feature ofreduced parasitic capacitance for the extension regions 7 due to the useof the T-shaped gate electrode structure. By providing the SiGepolycrystal layer 3 underneath the polysilicon layer 4 and by utilizingthe difference of oxidation rate between the polycrystal layer 3 and thepolysilicon layer 4, it is possible to form the desired T-shaped gatestructure by a mere single oxidation step. Associated with the use ofthe T-shaped gate electrode, the MOSFET of FIG. 2 is advantageous forproviding a silicide layer on the top part of the polysilicon layer 4.

[0047] It should be noted that the polycrystal layer 3 may contain C inaddition to Si and Ge. In this case, the polycrystal layer 3 is formedof a SiGeC mixed crystal. The use of the SiGeC mixed crystal furtherenhances effect of blocking the penetration of B. Further, thepolycrystal layer 3 may contain additional impurity elements such as B,P or As.

[0048] In the MOSFET of FIG. 2, it is also possible to remove thelateral oxide film 5 after the formation of the T-shaped gate electrodebut before the formation of the sidewall insulation films 6. By removingthe lateral oxide film 5, it is possible to control the formation of apunch-through stopper at the channel region with high accuracy. Itshould be noted that such a punch-through stopper is formed by an ionimplantation of B or As through the bottom notched region of theT-shaped gate electrode.

[0049] [First Embodiment]

[0050] Hereinafter, a fabrication process of a MOSFET according to afirst embodiment of the present invention will be described withreference to FIGS. 3A-3F.

[0051] Referring to FIG. 3A, a gate oxide film 12 is formed on a p-typeSi substrate 11 with a thickness of 3 nm, and a polycrystal SiGe layer13 is formed on the gate oxide film 12 with a thickness of 10-150 nm,preferably about 50 nm, by a low-pressure CVD process, while using SiH₄and GeH₄ as the source of Si and Ge. Further, a polysilicon layer 14 isdeposited on the polycrystal SiGe layer 13 with a thickness of 20-200nm, preferably about 100 nm, by a CVD process while using SiH₄ as thesource of Si. The SiGe polycrystal layer 13 may have a composition inthe range of Si₉₀Ge₁₀—Si₁₀Ge₉₀. In a preferred example, the SiGepolycrystal layer 13 may have a composition of Si₉₀Ge₁₀.

[0052] Next, an anisotropic etching process is applied to the layers 13and 14 thus formed such that there is formed a gate electrode structurehaving a gate length of 0.1 μm.

[0053] Next, in the step of FIG. 3B, the structure of FIG. 3A issubjected to a dry oxidation process conducted in an oxidizingatmosphere at 800° C. for 3 minutes, and there are formed oxide films 15on both lateral sidewalls of the gate electrode structure of FIG. 3A asrepresented in FIG. 3B. While not illustrated, it should be noted thatthe top surface of the polysilicon layer 14 is protected from oxidationby an SiN mask not illustrated.

[0054] During the oxidation process of FIG. 3B, it should be noted thatthe oxidation rate of the SiGe polycrystal layer 13 is much larger thanthe oxidation rate of the polysilicon layer 14 by twice or three times.Thus, the oxidation process proceeds much faster in the SiGe polycrystallayer 13 than in the polysilicon layer 14 and the lateral sidewall oxidefilm 15 has an increased thickness in the part covering the SiGepolycrystal layer 13 than in the polysilicon layer 14. For example, thelateral sidewall oxide film 15 may have a thickness of about 3 nm in thepart covering the polysilicon layer 14 and a thickness of about 10 nm inthe part covering the SiGe polycrystal layer 13.

[0055] Next, in the step of FIG. 3C, the lateral sidewall oxide film 15is removed by an aqueous solution of HF, and an ion implantation processof B is conducted into the substrate 11 as a punch-through stopper.

[0056] Next, in the step of FIG. 3D, an ion implantation process of As⁺ions 16 is conducted into the substrate 11 while using the polysiliconlayer 14 of the T-shaped gate electrode as a mask, and there are formeda pair of n-type diffusion regions 17 at both lateral sides of the SiGepolycrystal layer constituting the bottom part of the T-shaped gateelectrode with an offset therefrom.

[0057] Next, in the step of FIG. 3E, the structure of FIG. 3D is coveredby a CVD-SiO₂ film, followed by an etch-back process, and there areformed sidewall oxide films 18 at both lateral sides of the T-shapedgate electrode of FIG. 3D. Further, an ion implantation process of As⁺ions is conducted into the substrate 11 while using the sidewall oxidefilms 18 as a mask, and there are formed n⁺-type diffusion regions 20 inthe substrate 11 at the outer regions of the sidewall oxide films 18.

[0058] Next, in the step of FIG. 3F, the As⁺ ions thus introduced areactivated by applying a thermal annealing process. As a result of such athermal annealing process, the respective tip ends of the n-typediffusion regions 17 approach with each other to reach the location moreor less coincident to the lateral edges of the SiGe polycrystal layer13, and the offset between the tip end of the diffusion region 17 andbottom lateral edge of the T-shaped gate electrode is eliminated.Thereby, the overlap of the diffusion region 17 and the bottom part ofthe T-shaped gate electrode is minimized.

[0059] Next, a Co layer (not shown) is deposited on the structure ofFIG. 3E by a sputtering process with a thickness of 10 nm, followed by arapid thermal annealing process conducted in an N₂ atmosphere at 550° C.for 30 minutes, and there are formed cobalt silicide regions 21 on theexposed surface of the n⁺-type diffusion regions 20 and the top surfaceof the polysilicon layer 14 forming the T-shaped gate electrode.

[0060] After the formation of the cobalt silicide regions 21, theunreacted Co layer is removed by a wet etching process conducted for 20minutes in an etchant containing H₂SO₄ and H₂O₂ with a ratio of 3:1, andthe structure thus obtained is subjected to a rapid thermal annealingprocess conducted at 800° C. in an N2 atmosphere for 30 seconds, so asto convert the cobalt silicide layer 21 thus formed into alow-resistance silicide represented as CoSi₂.

[0061] As a result of such a process in the step of FIG. 3F,self-aligned ohmic electrodes are formed by the CoSi₂ layers 21respectively on the n⁺-type diffusion regions 20 and the polysiliconlayer 14.

[0062] According to the present invention, the T-shaped gate electrodeis formed easily and with high precision by employing the two-layer,polysilicon/SiGe structure for the gate electrode.

[0063] In view of the fact that the SiGe polycrystal layer 13constituting the bottom part of the T-shaped gate electrode provides ahigher activation rate of the impurity element, no depletion region isformed in the gate region in the vicinity of the interface to the gateinsulation film, even when a gate voltage is applied to the gateelectrode. Further, the T-shaped gate structure of the present inventionallows the use of salicide structure on the top part of the T-shapedgate electrode.

[0064] By removing the lateral sidewall oxide film 15 in the step ofFIG. 3C, the present embodiment enables a high-precision control whenforming the punch-through stopper structure.

[0065] [Second Embodiment]

[0066] FIGS. 4A-4C show the fabrication process of a MOSFET according toa second embodiment of the present invention, wherein those partscorresponding to the parts described previously are designated by thesame reference numerals and the description thereof will be omitted.

[0067] Referring to FIG. 4A, the structure corresponds to the structureof FIG. 3B of the previous embodiment, and the formation of thepunch-stopper structure is conducted in the step of FIG. 4A byconducting an ion implantation process of B.

[0068] After the formation of the punch-through stopper structure, thediffusion regions 17 are formed in the substrate 11 by an ionimplantation of As⁺ ions 16 while using the lateral sidewall oxide film15 as a self-aligned mask.

[0069] Next, in the step of FIG. 4B, the sidewall oxide films 18 areformed on the lateral sidewalls of the oxide films 15 by a CVD processand an etch-back process, and an ion implantation process of As⁺ ions 19is conducted into the substrate 11 to form the n+type diffusion regions20 while using the sidewall oxide films 18 as a self-aligned mask.

[0070] Further, the As⁺ ions introduced in the steps of FIGS. 4A and 4Bare activated in the step of FIG. 4C by applying a thermal annealingprocess to the structure of FIG. 4B, wherein such a thermal annealingprocess causes a movement of the tip end of the diffusion regions 17 tothe location more or less coincident with the bottom lateral edge of theT-shaped gate electrode as represented in FIG. 4C.

[0071] Further, the CoSi₂ ohmic electrodes 21 are formed on the n⁺-typediffusion regions 20 and on the polysilicon layer 14, similarly to theprevious embodiment.

[0072] According to the present embodiment, it is possible to reduce thenumber of fabrication steps by eliminating the step for removing thelateral sidewall oxide film 15.

[0073] [Third Embodiment]

[0074] FIGS. 5A-5C show the fabrication process of a MOSFET according toa third embodiment of the present invention.

[0075] Referring to FIG. 5A, a gate oxide film 32 is formed on a p-typeSi substrate 31 with a thickness of about 3 nm, and a polycrystal SiGelayer 33 is formed on the gate oxide film 32 with a thickness of about50 nm, by a low-pressure CVD process, while using SiH₄ and GeH₄ as thesource of Si and Ge. Further, a polysilicon layer 34 is deposited on theSiGe polycrystal layer 33 with a thickness of about 100 nm by a CVDprocess while using SiH₄ as the source of Si. The SiGe polycrystal layer13 may have a composition of Si₉₀Ge₁₀.

[0076] Next, an anisotropic etching process is applied to the layers 13and 14 thus formed such that there is formed a gate electrode structurehaving a gate length of 0.1 μm.

[0077] In the step of FIG. 5A, an ion implantation process of B isconducted selectively to the part of the substrate 31 adjacent to thelateral edge of the gate electrode 33 for forming the punch-throughstopper structure, and an ion implantation process of As⁺ ions 35 isconducted while using the polysilicon upper gate electrode 34 as a mask.As a result of the ion implantation process of the As⁺ ions 35, n-typediffusion regions 36 are formed in the substrate 31 in alignment withthe gate electrode on the gate insulation film 32.

[0078] Next, the structure of FIG. 5A is subjected to a dry oxidationprocess in the step of FIG. 5B, and there is formed a lateral sidewalloxide film 37 on the lateral sidewalls of the polysilicon layer 34 andthe SiGe polycrystal layer 33. Because of the increased oxidation rateof the SiGe polycrystal layer 33, the lateral sidewall oxide film 37 hasan increased thickness in the part covering the sidewall of the SiGepolycrystal layer 33 than the part covering the sidewall of thepolysilicon layer 34. As a result, there is formed a T-shaped gateelectrode as represented in FIG. 5B.

[0079] With the formation of the lateral sidewall oxide films 37, therespective tip ends of the n-type diffusion regions 36 approach witheach other and to the location more or less coincident to the lateraledges of the SiGe polycrystal layer 33 as represented in FIG. 5B.

[0080] Next, in the step of FIG. 5C, a pair of sidewall oxide films 38are provided on the structure of FIG. 5B by depositing a CVD-SiO₂ filmand applying an etch-back process thereto. Further, an ion implantationprocess of As⁺ is conducted into the substrate 31 while using thesidewall oxide films 38 as a mask. As a result, n⁺-type diffusionregions 39 are formed in the substrate 31 at the region outward to then-type diffusion regions 36.

[0081] Further, CoSi₂ ohmic electrodes 40 are formed on the exposedsurface of the n⁺-type diffusion regions 39 and on the polysilicon layer34 of the T-shaped gate electrode.

[0082] According to the present embodiment, it is possible to conductthe annealing process for forming the n⁺-type diffusion regions 39 andthe CoSi₂ ohmic electrodes 40 simultaneously.

[0083] [Fourth Embodiment]

[0084]FIG. 6 shows the construction of a MOSFET according to a fourthembodiment of the present invention, wherein those parts correspondingto the parts described previously are designated by the same referencenumerals and the description thereof will be omitted.

[0085] Referring to FIG. 6, the MOSFET of the present embodiment uses asubstrate 110 having an SOI (silicon-on-insulator) structure.

[0086] Thus, the substrate 110 includes an oxide substrate 110A and ap-type Si layer 110B formed thereon, and the MOSFET is formed on such ap-type Si layer 110B.

[0087] According to the present embodiment, it becomes possible tominimize the junction capacitance for the diffusion regions 20, and theoperational speed of the MOSFET is improved further.

[0088] In the description heretofore, it should be noted that the SiGepolycrystal layer 13 or 33 may be formed by an ion implantation of Geinto a polysilicon layer. Further, the SiGe polycrystal layer 13 or 33may further contain C. Particularly, the SiGe polycrystal layercontaining C with 1.5 at % is effective for blocking the penetration ofB.

[0089] Further, the SiGe polycrystal layer 13 or 33 may containadditional elements such as B, P or As for electric conductivity.

[0090] The oxidation process used in the step of FIG. 3B is not limitedto a dry oxidation process but a wet oxidation process may be used also.

[0091] Further, the SiN mask layer explained with reference to the stepof FIG. 3B for avoiding the oxidation of the top surface of thepolysilicon layer 14 may be eliminated in the first embodiment, as anyoxide film formed on the top surface of the polysilicon layer 14 isremoved during the etching process of FIG. 3C.

[0092] The present invention is effective not only for the N-channel MOStransistors explained heretofore, but also for P-channel MOS transistorsthat uses a B-doping for the gate electrode for constructing a CMOScircuit operating at low voltages.

[0093] Further, the present invention is not limited to the embodimentsdescribed heretofore, but various variations and modifications may bemade without departing from the scope of the invention.

What is claimed is:
 1. A semiconductor device, comprising: a substrateincluding a semiconductor layer at least on a top part thereof; a gateinsulation film provided on said semiconductor layer; and a gateelectrode provided on said gate insulation film, said gate electrodecomprising a first polycrystal layer in contact with said gateinsulation film, said first polycrystal layer containing at least Si andGe, and a second polycrystal layer provided on said first polycrystallayer, said first polycrystal layer having a reduced lateral size ascompared with said second polycrystal layer, said first and secondpolycrystal layers thereby forming a T-shaped gate electrode.
 2. Asemiconductor device as claimed in claim 1, wherein said firstpolycrystal layer further contains C.
 3. A semiconductor device asclaimed in claim 2, wherein said first polycrystal layer contains C witha concentration of about 1.5 at %.
 4. A semiconductor device as claimedin claim 1, wherein said first polycrystal layer is doped with any of B,P and As.
 5. A semiconductor device as claimed in claim 1, wherein saidsemiconductor device has a bulk silicon substrate.
 6. A semiconductordevice as claimed in claim 1, wherein said semiconductor device has asilicon-on-insulator substrate.
 7. A method of fabricating asemiconductor device, comprising the steps of: forming a gate insulationfilm on a substrate, said substrate including a semiconductor layer atleast on a top part thereof; depositing a first polycrystal layercontaining at least Si and Ge on said semiconductor layer; depositing asecond polycrystal layer of Si on said first polycrystal layer;patterning said first and second polycrystal layers to form a gateelectrode defined by a pair of sidewalls; and applying an oxidationprocess to said first and second polycrystal layers such that said firstand second polycrystal layers undergo oxidation at said both sidewalls.8. A method as claimed in claim 7, further comprising the step ofremoving an oxide film formed in said step of applying said oxidationprocess.
 9. A method as claimed in claim 7, wherein said firstpolycrystal layer is formed by a CVD process while using SiH₄ and GeH₄as respective sources.
 10. A method as claimed in claim 7, wherein saidfirst polycrystal layer is formed by conducting an ion implantationprocess of Ge into a polysilicon layer.